The present invention relates to binary full adder stages and to their fabrication from two binary half adder stages which receives two input signals and generates a partial sum and a partial carry therefrom.
It is well known that binary full adder stages are built up of two half adder stages that each receive two inputs and perform an Exclusive OR function thereon to generate a partial sum and an AND function thereon to generate a partial carry. It is suggested in Morgan et al, U.S. Pat. No. 3,074,639 that using a special Exclusive OR network in each half adder stage, a full adder stage can be implemented in two logic delays. However, such special purpose Exclusive OR circuits are not always available in the circuit family being employed to implement the adder and are generally slower than standard logic blocks in performing the half adder function. In addition, in large scale integration (LSI) custom designed chips are expensive and need high usage to be justified.
Bundling is a logic design technique to save logic circuits. This technique has been employed in adders as evidenced by an article entitled "Decimal Adder Carry Circuits", appearing on page 382 of the August 1969 issue of the IBM Technical Disclosure Bulletin.